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Experience 5G Revolution with VVDN Experience 5G Revolution with VVDN

Experience 5G Revolution with VVDN

Industry Leading Experts with Expertise Across IPs and Wireless Capabilities


In this revolutionary digital era where speed is playing an impeccable role, VVDN is working to deliver next-generation 5G acceleration solutions that will not only implement the complex modules of 5G infrastructure but also position VVDN well ahead in 5G network solution space. With our deep wireless capabilities, we are offering cutting edge solutions to industry leaders that help in delivering the promise of 5G which is increased performance, deployment flexibility, and cost-effectiveness. VVDN has the experience, skills and solutions to secure a successful evolution to 5G for mobile service providers as well as OEMs and enables them to unlock the full 5G potential. Our industry leading experts are here to turn your 5G visions into a real business.

Evolution of Wireless

VVDN, with ample experience in wireless communication technologies, great hardware capabilities and focused approach towards final solutions, is contributing to accelerate the deployment of 5G networks worldwide. Preparing for 5G technology includes modernizing existing mobile network infrastructure for radio, core and transport networks. 5G wireless network system will deliver a high level of performance with efficiency which in turn enables the new user experience and will open new highways towards different business use cases and opportunities









Digital 1990

2G (GSM)

Data Services 14.4kb/s




Data/PS 3G (UMTS)


Video Calling and Streaming
3.1 Mb/s


Full IP


4G (LTE)

4G (LTE)

HD Video Conferencing & Worldwide Roaming 300 Mb/s




5G (LTE Advanced)


Super Fast Internet
Low Latency Network
AI/ML Applications
>1 Gb/s


VVDN Offerings

With our expertise in the 5G physical layer and FPGA, we are capable of delivering multiple flavors of NG-RAN deployment considering standard specifications for communication between distributed functionality of NG-RAN (e.g. FAPI/nFAPI, CPRI/eCPRI, etc). VVDN’s 5G IPs (FPGA, Software & Hardware) on Fronthaul and Layer 1 (High PHY & Low PHY) are the perfect vehicles to help build robust 5G network infrastructure.

It is an oRAN/xRAN over eCPRI Solution for 7-2x Split up with PCIe Gen3.0 x8 host interface to the High-PHY SW layer. High PHY runs in the host and IQ samples can be transported over PCIe interface to FPGA.1PPS input is provided for frame synchronization. It can support block floating-point compression and modulation compression and the design is scalable to support multiple Fronthaul.

Fronthaul (ORAN over eCPRI)

VVDN High PHY offload solution is based on option 7.2 functional split. This split option is aimed at making RU simple by moving more complex blocks to DU with FPGA interfaced with x86 via PCIe. The FPGA contains a separate queue for both downlink and uplink processing where high CPU intensive tasks will be offloaded. This includes LDPC encoding/decoding, rate matching, HARQ combine, etc.

High PHY + Fronthaul (ORAN over eCPRI)

VVDN Low PHY solution is based on option 8 functional split. This split option is aimed at making RU simple by moving more complex blocks to DU. The Low PHY includes iFFT and CP insertion in the downlink path. The uplink path involves CP removal and FFT to convert the time domain OFDM symbols to IQ samples for sending through CPRI over Ethernet.

5G Small Cell Solution

By offloading CPU-intensive functions such as virtual switching, PDCP ciphering tasks and IPSEC tunneling from the general-purpose processors to a network interface card, the solution successfully delivers a great performance improvement and CPU core savings. This platform offloads and accelerates virtualized wireless eNode/gNB platforms and moves processing workloads from host processors to increase throughput, lower latency and offload resources from general-purpose processing elements.

PDCP Air-Crypto Acceleration

VVDN’s OVS IP is a hardware-accelerated full line rate open flow switch implemented on the Xilinx FPGA platform. The OVS flow table entries are maintained in FPGA on-chip memory. When a flow matches the entry in the flow table, the respective action will be taken. If a flow entry miss occurs, the packet will be forwarded to OVS kernel module which will process the header information and the action will be taken.

  • 5G CU/DU
  • Small Cell
  • RRU
  • Fronthaul Gateway
1. 5G CU/DU

o-vDU /o-vCU on COTS Server


Telco industries are transforming into a Network Function Virtualization (NFV) approach to make deployments more flexible, efficient use of underlying hardware and to reduce the total cost of ownership (TCO).

o-CU and o-DU, when implemented as NFV on COTs, enable the telco functionalities.

For a telco-grade deployment, each NFV needs to attain a Service Level Agreement (SLA). This is achieved by placing focus on user data plane in terms of throughput, packet loss guarantees, latency effects.

In a typical deployment, L2/L3 up to higher layers of L1 (Hi-PHY) will be implemented as software layers with a hardware accelerator

An O-RAN 7-2x split up will be used between o-RU (O-RAN Radio Unit) which will be at the site and the o-DU which is virtualized in a Telco cloud. With this split-up, IQ sampled can be transported from o-DU to o-RU via optical fiber over a distance of 20 km

VVDN has strong expertise in this domain and has solutions available on Hi-PHY and various acceleration block which is required to build this infrastructure. With the proven excellence and extensive experience VVDN provides the following solutions:

  • -Fronthaul
  • -LDPC/Polar Acceleration (Other Hi-PHY layers can be supported)
  • -OVS Offload
  • -Air Crypto Acceleration
  • -Full System Integration
2. Small Cell
The 5G vision is to address the requirements of gigabit data rate, ultra-low latency, massive connectivity, and coverage. Migration from the previous standard to 5G would be done in such a way that both technologies will co-exist for some period. One of the practical solutions for early NR deployment would be such that LTE will take the role of master and NR, the role of the small or secondary cell. These configurations can be deployed with the existing LTE infrastructure.
VVDN has the L1 PHY layer implemented in RFSoC. The data and control transfer from L2/L3 in CPU to L1 in RFSoC is via a PCIe interface.
Benefits of Small Cell:

To provide reliable and enhanced coverage

To achieve better spectral efficiency

To improve overall network performance & capacity

To cut down the transmission cost-per-bit

3 .RRU
We are developing a 4T4R NR RU which is O-RAN 7-2a based with the following specifications:

Bandwidth: 5G NR:100MHz

Band: 3.5 GHz

Output power: 0dBm/channel

EVM: 64QAM EVM less than 5%, 256QAM EVM less than 3.5%

Receiving sensitivity: ≤-93.5dBm

4 .Fronthaul Gateway
The solution can convert eCPRI traffic to the individual CPRI lanes. The unit will perform Low PHY functionalities to convert frequency domain IQ samples from eCPRI to time-domain samples and transport over CPRI & vice versa. The design is based on the O-RAN standard.


IRYA is a Half Height Half Length (HHHL) PCI Express® Gen3 x16 compliant card designed to accelerate compute-intensive networking applications (wired as well as wireless). The FPGA in the IRYA can be configured using the Vivado tool through the USB port. This card is based on XCVU7P FPGA. IRYA has been successfully tested for executing OvS (Open vSwitch) and Cryptography (Network Accelerator) as the reference solutions.

ADYA Telco NIC + Acceleration card

ADYA TelcoNIC + Acceleration card

ADYA is a Full Height Half Length (FHHL) card, built around Xilinx Zync Ultrascale+ MPSoC & RFSoC, having two SFP28 and x16 PCIe interface bifurcated to two x8 interfaces. ADYA has been successfully tested for executing Layer 1 (High PHY & Low PHY) and Fronthaul as the reference solutions.

SAHA Acceleration Card

SAHA Acceleration Card

SAHA is a single slot Half Height Half Length card (HHHL). SAHA Telco NIC is built around Xilinx Zync Ultrascale+ RFSoC. The RFSoC contains hard SDFEC blocks to offload high CPU intensive tasks like LDPC encode/decode. This acceleration card is interfaced to CPU via PCIe x16.

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